Novel Test Structures for 2D-Mesh NoC with Evaluation on the Coverage-driven & VMM-based Testbench

NoC(Network-on-Chip) has been proposed as a new solution to deal with the global communication problem of complex SoC(System-on-Chip). However, there are many difficulties in testing and verification for NoC. We propose novel test architectures for 2D-Mesh topology NoC to improve the parallelism of tranferring test packets. The testing efficiencies of different structures are evaluated under a coverage-driven and hierarchical NoC testbench, which is based on the VMM verification methodology and SystemVerilog language. The evaluation results of testing cost, testing time and hardware overhead show that the shortening of transmission path and parallel testing effectively decreases the power consumption and testing time. Furthermore, one of the test structures can be proved to the optimal scheme.